(a) Field of the Invention
The present invention relates of a semiconductor device having an ESD (electrostatic-discharge) protective circuit and, more particularly, to a semiconductor device having an ESD protective circuit for protecting the internal circuit of the semiconductor device against the ESD breakdown.
(b) Description of the Related Art
A semiconductor integrated circuit (or semiconductor device) fabricated on a semiconductor substrate generally includes semiconductor elements such as MOSFETs. It is known that MOSFETs are liable to ESD breakdown wherein an excessively high input voltage such as an electrostatic pulse voltage enters and damages the semiconductor device. Thus, a technique for protecting the semiconductor elements in the semiconductor device against the damage caused by and ESD breakdown is essential to the semiconductor device. A large number of proposals have been made and used heretofore for the technique.
Along with the higher integration of the semiconductor device as well as developments for lower operational voltage and lower power dissipation thereof, the semiconductor elements constituting the semiconductor device have more and more smaller dimensions and thereby increase in number per unit area. This leads to increase in the probability of the ESD breakdown of the semiconductor elements, especially of the MOSFETs, having smaller dimensions and packed with a higher density.
In the semiconductor device including semiconductor elements having smaller dimensions the operational voltage of the peripheral circuit is generally higher than the operational voltage of the internal circuit. For example, the peripheral circuit operates on a 5-volt power source whereas the internal circuit operates on a 2-volt power source. Accordingly, the gate insulation films of the MOSFETs have a larger thickness in the peripheral circuit than in the internal circuit.
In addition, a system-on-chip configuration having a combination of memory, logic and analog circuits is more and more employed in the semiconductor devices. Among others, the combination device having a flash memory or nonvolatile memory and a logic circuit includes a larger number of floating gate MOSFETs. The floating gate MOSFETs are not used in a semiconductor device having no non-volatile memory heretofore.
A conventional ESD protective circuit for protecting a semiconductor device is described in JP-A-63-202056. FIG 1A shows the described ESD protective circuit and FIG. 1B shows a schematic sectional view thereof.
In FIG. 1A, an input 72 is connected to an input terminal 71 at one end, and also is connected at the other end to a gate of a MOSFET in an internal circuit not shown. An ESD protective nMOSFET 73 is connected between the input line 72 and the ground line VSS, the nMOSFET 73 having a gate maintained at the ground potential (VSS potential).
The nMOSFET 73 as described above has large dimensions in general. Although the ESD protective device includes the single nMOSFET 73 therein, the nMOSFET 73 acts as a bipolar transistor upon input of a high-voltage pulse. Thus, in FIG. 1A, a parasitic bipolar transistor 74 is depicted between the input line 72 and the ground line.
In FIG. 1B, the protective nMOSFET 73 is formed on a p-type semiconductor substrate 75, wherein an n+-diffused region 76 constituting a drain and connected to the input terminal 71 is surrounded by an overlying gate electrode 77, which is surrounded by another n+-diffused region 78 constituting a source.
The parasitic NPN bipolar transistor 74 depicted by dotted lines includes a base at the semiconductor substrate 75, an emitter at the source 78 of the nMOSFET 73 and a collector at the drain 76 of the nMOSFET 73. It is to be noted that the source 78 is connected to the ground line VSS, and the input terminal 71 implemented by a metallic pad is formed on the drain 76.
In the conventional semiconductor device of FIGS. 1A and 1B, if an excessively high input voltage is applied to the drain 76 through the input lien 71, an avalanche breakdown first occurs at the p-n junction formed just under the gate electrode 77 between the semiconductor substrate 75 and the drain 76. The avalanche breakdown generates a large number of positive holes as majority carriers. The positive holes thus generated raises the potential of the semiconductor substrate 15 to a positive side, which allows the parasitic bipolar transistor to operate in a snapback mode. The snapback mode of the parasitic bipolar transistor turns ON the nMOSFET, which discharges and lowers the potential of the drain 76 caused by the excessively high input voltage.
The avalanche breakdown of the p-n junction is generally local in the nMOSFET having larger dimensions. In this case, the bipolar mode caused by the avalanche breakdown remains in the limited area of the nMOSFET here the breakdown first occurred. Thus, the local area at which the avalanche breakdown first occurred is likely to be damaged by the ESD breakdown. The locality of the bipolar mode of the nMOSFET is enhanced by an LDD structure of the diffused regions, whereby the local breakdown is more likely in the MOSFET having the LDD structure.
In addition, the nMOSFET is liable to damages by a breakdown in the gate insulation film thereof. The breakdown in the gate insulation film occurs more frequently in the case of a MOSFET having smaller dimensions. The breakdown in the gate insulation film is considered due to the potential rise of the semiconductor substrate caused by the avalanche breakdown generating a large number of positive holes. The positive holes entering the gate insulation film 17 from the semiconductor substrate 15 more raises the potential of the gate insulation film compared to the semiconductor substrate 15.
FIG. 2 shows another conventional ESD protective circuit, wherein an input line 82 is connected to an input terminal 81 and also connected to a gate of MOSFET in an internal circuit not shown. The protective circuit includes a pMOSFET 83 connected between the high-voltage power source line (VCC line) and the input line 82, and an nMOSFET 84 connected between the input line 82 and the ground line VSS. The pMOSFET 83 has a gate and a backgate (or well) both connected to the VCC line. The nMOSFET 84 has a gate and a backgate (or well) both connected to the ground line VSS.
If an excessively high input voltage having a positive polarity is applied to the input terminal 81, positive holes are generated due to the avalanche breakdown of the p-n junction formed on the drain of the nMOSFET 84. The positive holes raises the potential of the semiconductor substrate thereby allow the nMOSFET 84 to operate in a bipolar mode and cause a snapback breakdown. Similarly, if an excessively high voltage having a negative polarity is applied to the input terminal 81, electrons are generated due to the avalanche breakdown of the p-n junction formed on the drain of the pMOSFET 83. The electrons lower the potential of the semiconductor substrate, thereby allowing the pMOSFET to operate in a bipolar mode and cause a snapback breakdown. It is to be noted that the p-n junction on the drain is forward-biased if either the excessively high voltage as described above is applied to the input terminal 81. The ESD occurs through the p-n junction constituting a diode.
In the conventional protective circuit of FIG. 2, if a high input voltage which does not cause the avalanche breakdown is applied to the input terminal, the protective circuit cannot respond to the high input voltage. Since the avalanche breakdown voltage cannot be adjusted to a satisfactory lower level, it is difficult to obtain a protective circuit of FIG. 2 having a desired operational voltage. In contrast, it is possible to obtain a protective circuit of FIG. 1A having a desired operational voltage because a smaller gate length and a smaller thickness of the gate insulating film allow the MOSFET to respond to a lower pulse voltage and generate an ESD.
In the current semiconductor devices, the withstand voltage of the p-n junction has a tendency to exceed the expected voltage defined by the scaling low of the finer pattern of the MOSFETs. In addition, in the nonvolatile memory such as a flash EEPROM, the programming/erasing voltage is considerably higher than the power source voltage. Accordingly, a breakdown of the gate insulation film often occurs before the avalanche breakdown of the p-n junction.
As a common problem in the protective circuits of FIGS. 1A and 2, the MOSFETs provided in the protective circuits have larger dimensions compared to the other MOSFETs in the internal circuit. For example, the MOSFET in the protective circuit has a gate length (L) of 1 xcexcm, and a gate width (W) of 500 xcexcm. For this purpose, the MOSFET in the protective circuit includes ten unit MOSFETs in parallel each having a gate electrode having a gate width of 50 xcexcm, for example. In this configuration, the local avalanche breakdown has a tendency to activate a specific unit MOSFET among the ten unit MOSFETs, whereby the breakdown current concentrated at the single unit MOSFET damages the same and thus the protective circuit itself.
FIG. 3 shows another conventional protective circuit, wherein an nMOSFET 93 is connected between the input line 92 and the ground line VSS, the nMOSFET 93 having a gate electrode connected to the I/O line 92 via a capacitor 94 and to the ground line VSS via a resistor 95.
In the protective circuit of FIG. 6, if an electrostatic high-voltage pulse is applied to the I/O line 92, the gate potential of the nMOSFET 93 is momentarily raised via the capacitor 94, whereby the nMOSFET 93 is turned ON to effect electrostatic discharge (or ESD). By setting the resistance of the resistor 95 at a suitable value, the operation voltage of the nMOSFET 93 can be adjusted.
The protective circuit of FIG. 3 is more effective for controlling the operational voltage compared to the protective circuits of FIGS. 1A and 2 wherein the avalanche breakdown voltage of the p-n junction is difficult to control. However, the protective circuit of FIG. 3 has a drawback wherein this type of nMOSFET cannot be used as an output buffer.
In view of the above problems in the conventional techniques, it is an object of the present invention to provide a semiconductor device having an ESD protective circuit which is capable of protecting the internal circuit of the semiconductor device against an ESD breakdown, with a limited area for the protective circuit and a simplified structure.
The present invention provides a semiconductor device including a semiconductor substrate, and internal circuit formed on the semiconductor substrate, and a protective circuit for protecting the internal circuit against an electrostatic discharge breakdown, the protective circuit including at least one first floating gate MOSFET, the first floating gate MOSFET having a source-drain path connected between an input/output line (I/O line) and a constant potential line, a control gate connected to the I/O line, a floating gate connected to the constant potential line or a first line.
The present invention also provides a semiconductor device including a semiconductor substrate, an internal circuit formed on the semiconductor substrate and a protective circuit for protecting the internal circuit against an electrostatic discharge breakdown, the protective circuit including at least one first floating gate MOSFET, the first floating gate MOSFET having a source-drain path connected between a first I/O line and a second I/O line, a control gate connected to the first I/O line, a floating gate connected to a ground line.
In accordance with the semiconductor device of the present invention, the floating gate MOSFET first operates in a pinch-off mode due to the potential rise of the control gate receiving an excessively high input voltage, thereby generating positive holes in the semiconductor substrate. The positive holes thus generated trigger the floating gate MOSFET to operate in a uniform bipolar mode due to the presence of a parasitic bipolar transistor in the floating gate MOSFET. The uniform bipolar mode operation of the floating gate MOSFET allows a uniform snapback breakdown thereof, whereby the protective circuit can protect the internal circuit against the excessively high input voltage which may have a relatively lower voltage compared to a clock signal, for example, without causing a damage of the protective device itself.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.